In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative to the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (“SDRAMs”), synchronous static random access memories (“SSRAMs”), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device are typically synchronized to external operations. For example, commands are placed on a command bus o f the memory device in synchronism with the external clock signal, and the memory device must latch these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to clock the commands into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. In the present description, “external” refers to signals and operations outside of the memory device, and “internal” refers to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is minimal, timing within the memory device can be easily synchronized to the external timing. However, with higher frequency clock signals, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result of inherent delays, the commands applied to the memory device may no longer be valid by the time the internal clock signal clocks the latches. Additionally, as the frequency of the external clock increases, variations in the duty cycle of the clock signal introduce a greater duty cycle error. An ideal duty cycle for a clock signal is typically 50 percent. That is, over the period of a clock cycle, the clock signal is HIGH for 50 percent of the period. As the period of the clock signals become shorter due to the increased clock frequency, a clock variation that results in a subtle shift in duty cycle, and which can be ignored at a lower clock frequency, may result in a much more significant shift in the duty cycle of the higher frequency clock signal. In such instances, if the duty cycle of the clock signal is left uncorrected, timing errors may cause the memory device to fail.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay locked loops (“DLLs”) with duty cycle correction (“DCC”) circuits, as will be appreciated by those skilled in the art. To correct duty cycle errors in clock signals, DCC circuits have been used to generate clock signals having a 50 percent duty cycle. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another.
FIG. 1 illustrates a conventional clock generator 100 having a DLL 110 and a DCC circuit 120. An input clock signal CLK represents an external clock signal applied to the DLL 110. As will be explained in more detail below, the DLL 110 generates an output clock signal CLK0 that is synchronized with the CLK signal. Due to the design of conventional DLLs, a duty cycle error in the CLK signal is carried through to the CLK0 signal. Thus, the CLK0 signal is provided to the DCC circuit 120 to correct any duty cycle error and generate an output clock signal CLKSYNC that is synchronized with the CLK0 signal and has a duty cycle corrected to 50 percent.
FIG. 2 illustrates the conventional DLL 110 and the DCC circuit 120 in greater detail. The DLL includes an input buffer 202 that provides a buffered clock signal CLKBUF in response to receiving the CLK signal. The CLKBUF signal is delayed relative to the CLK signal due to a propagation delay of the input buffer 202. The CLKBUF signal is provided to a variable delay circuit 204 that has a variable delay controlled by an adjustment signal DADJ1 generated by a shift register 206. The output clock signal of the variable delay circuit 204 is the CLK0 signal, which is delayed relative to the CLKBUF signal by the variable delay. An output clock signal CLKSYNC is fed back through a model delay 208 to provide a feedback clock signal CLKFB1. The model delay 208 adds a delay to the CLKSYNC signal, which is approximately equal to the total delay of the input buffer 202, an output buffer 240 in the DCC 120, and the delay that is injected by the DCC circuit 120 to the CLK0 signal and a CLK180 signal. A phase detector compares the CLKBUF and CLKFB1 signals, and generates a control signal DCONT1 for the shift register 206 in response to the phase difference between the CLKBUF and CLKFB1 signals. The variable delay circuit 204 is adjusted until the variable delay is sufficient to synchronize the CLKBUF and CLKFB1 signals. When the CLKBUF and CLKFB1 signals are in phase, the DLL 110 is said to be “locked.” Under this condition, the timing of the CLK0 signal is such that the delay of the output buffer 240 is accommodated, and a clock signal output by the output buffer 240 would be in phase with the CLK signal. As known in the art, when the CLKBUF and CLKFB1 signals are in phase, the delay of the DLL feedback loop, generally defined by the variable delay 204 and the model delay 208, is a multiple of the period TCLKBUF of the CLKBUF signal. That is, the feedback loop delay is equal to n*TCLKBUF, where “n” is an integer value.
As previously mentioned, the CLK0 signal is provided to the DCC circuit 120 for duty cycle correction. The DCC circuit 120 includes a first variable delay 230 and a second variable delay 232, which are coupled in series. An output clock signal CLKFB2 of the variable delay 232 is compared with the CLK0 signal by a phase detector 238. The phase detector 238 generates a control signal DCONT2 that is provided to a shift register 234. The shift register 234 generates an adjustment signal DADJ2 based on the DCONT2 signal that is used to adjust both the variable delay 230 and the variable delay 232 to the same delay. When the variable delays 230, 232 have been adjusted so that the phase difference between the CLK0 and CLKFB2 signals is an odd multiple of the clock period of the CLK0 signal an output clock signal CLK180 from the first variable delay 230 is 180 degrees out of phase from the CLK0 signal. As known in the art, the delay of the feedback loop for the DCC circuit 120, which is generally defined by the variable delays 230 and 232, is equal to one period of the CLK0 signal. Thus, one-half the loop delay, that is, the delay of one of the variable delays 230 , or 232, will provide a delay equal to one-half the period of the CLK0 signal, which is a clock signal 180 degrees out of phase from the CLK0 signal. The CLK0 and CLK180 signals are used by the output buffer 240 to generate the CLKSYNC signal, which is synchronized with the CLK signal and has a corrected duty cycle.
The conventional clock generator 100 places the DLL 110 and DCC circuit 120 in series with each other. This arrangement requires a clock signal to propagate through a plurality of adjustable delay lines, each of which have an adjustable delay that is potentially affected by such factors as the consumption of power or space, and by the operating limitations of the circuit.
Although the conventional clock generator 100 can successfully generate a synchronized clock signal having a 50% duty cycle, the conventional arrangement of the DLL 110 and the DCC circuit 120 is susceptible to several issues. One issue is clock jitter. Clock jitter is exhibited as small variations in the phase of the output clock signal that is generated by the clock generator 100. Clock jitter can be caused by small fluctuations or variations in the delay times of the delay stages found in adjustable delay lines, such as in the DLL 110 and the DCC circuit 120. As the delay times of the delay stages fluctuate, the resulting clock signal will drift or “jitter.” The fluctuations in delay time can be caused by power supply noise, which affects the delay time of each active delay stages of an adjustable delay line. In a conventional arrangement of the DLL 110 and the DCC circuit 120, such as that shown in FIGS. 1 and 2, having multiple adjustable delay lines (such as adjustable delay lines 204, 230, 232) coupled in series can compound a clock jitter problem. That is, a clock signal output by a first adjustable delay line will have clock jitter, and is propagated through a second adjustable delay line, which also injects jitter. The resulting clock signal output by the second adjustable delay line will have a cumulative clock jitter from both the first and second delay lines. Propagating the clock signal through one more adjustable delay line will only result in generating a clock signal having yet more clock jitter.
Moreover, the cascaded structure of variable delays results in relatively high power consumption, in addition to the problems with jitter as previously described, that can be compounded by the power supply noise potentially occurring at each stage of the delay, making an undesirable situation even worse.
Other issues with the arrangement of the DLL 110 and the DCC circuit 120 of the clock generator 100 are slowness of operation and cumbersome size. The conventional clock generator 100 is slow because two different feedback loops must be locked in sequence before an acceptable CLKSYNC signal is generated. That is, in one arrangement, upon start up, the DCC 120 is synchronized before the DLL 110 is activated to provide a clock signal having the appropriate delay relative to the CLK signal. Alternatively, the DLL 110 is locked to generate a synchronized clock signal before the DCC 120 is activated for duty cycle correction. It may take the DLL 110 by itself several hundred clock cycles to obtain lock and generate a synchronized CLK0 signal. The DCC circuit 120 then takes additional time to adjust the variable delays 230 and 234 to synchronize the CLK0 signal and the CLKFB signal to provide a suitable CLK180 signal. The time for the DCC circuit 120 to lock can add a significant amount of time to the already lengthy time it takes to lock the DLL 110.
The clock generator 100 is cumbersome because the circuit includes nearly two complete DLLs. That is, a clock signal must propagate through three different variable delay circuits 204, 230, 232 of similar delay length, two phase detectors 210, 238, and two shift registers 206, 234. A variable delay typically takes up a relatively large amount of space on a semiconductor substrate on which the clock generator and other components of a memory device are formed. Having multiple variable delays of similar delay length only exacerbates the issue and can be undesirable where the general design goal is reducing circuit size.
Therefore, there is a need for an alternative clock generator that combines the functions of a DLL 110 and DCC circuit 120 that reduces the size of the circuit, supply-induced noise and operating limitations, while improving circuit performance and clock jitter performance.